1. Field
The embodiments discussed herein are directed to a buffer circuit permitting an input signal to pass corresponding to an output control signal or prohibiting a passage of the input signal and a control method thereof.
2. Description of Related Art
As disclosed in Japanese Laid-open Patent Application No. 62(1987)-020423 and Japanese Laid-open Patent Application No. 2000-232350, there has been known a buffer circuit which permits an input signal to pass corresponding to an output control signal or prohibits a passage of the input signal. The Japanese Laid-open Patent Application No. 62(1987)-020423 has described a buffer circuit which comprises a first logical gate circuit in which a drive MOSFET on a reference potential side is placed in series so as to receive an output control signal and a signal to be sent to an external terminal, a second logical gate circuit in which a drive MOSFET on a reference potential side is placed in parallel so as to receive the output control signal and a signal to be sent to an external terminal and an output circuit comprising P channel MOSFET and N channel MOSFET which are driven to OFF state complementarily following an output signal of the first and second logical gate circuits or altogether.
The above-mentioned buffer circuit prevents the P channel MOSFET and the N channel MOSFET of the output circuit from being turned to ON state at the same time by using a time difference according to a difference of potential between a logic threshold voltage of the first logical gate circuit in which the drive MOSFET on the reference potential side is placed in series and a logic threshold voltage of a second logical gate circuit in which the drive MOSFET on the reference potential side is placed in parallel. Consequently, the above-mentioned buffer circuit can prevent a through current from flowing in the P channel MOSFET and N channel MOSFET.
The Japanese Laid-open Patent Application No. 2000-232350 has described a buffer circuit which turns a signal outputted by an output control circuit to a signal converting portion to a low level regardless of a value of data signal when it is controlled not to output any data signal from an output circuit by an enable signal which is an output control signal.
In the above-mentioned buffer circuit, the signal converting portion sends a high level signal to a gate of a P channel MOS transistor of the output circuit corresponding to the low level signal and further sends a low level signal to a gate of an N channel MOS transistor so as to turn both the transistors to OFF state. Consequently, in the above-mentioned buffer circuit, the P channel MOS transistor and the N channel MOS transistor are not turned to ON state at the same time, thereby preventing a through current from flowing to both the transistors.
A buffer circuit 100 shown in FIG. 6 includes gate voltage control circuits 120A, 120B for controlling each gate voltage of a P type channel transistor M1 and an N type channel transistor M2 which output a data signal to be inputted to an enable control input terminal (IN2) from a data output terminal (OUT1). In the gate voltage control circuit 120A, a current drive capacity of a P type channel transistor M3 is set larger than a current drive capacity of an N type channel transistor M4. Further, in the gate voltage control circuit 120B, a current drive capacity of an N type channel transistor M6 is set larger than a current drive capacity of a P type channel transistor M5.
The above-mentioned buffer circuit 100 operates as follows if a data signal changes from a low level to a high level when a circuit is so controlled that a low level enable signal is inputted from the enable control input terminal (IN2) and a data signal inputted from the data input terminal (IN1) is outputted from the data output terminal (OUT1).
In the above-mentioned buffer circuit 100, when a low level enable signal C is inputted from the enable control input terminal (IN2) and a high level data signal A is inputted from the data input terminal (IN1) in a period of time from 0 to t1 in FIG. 7 as shown in the Figure, a high level signal and a low level signal are inputted to a NAND gate circuit NAND. Reference numerals 41, 43 in the Figure indicate inverters. The NAND gate circuit NAND outputs a high level signal to each gate of the P type channel transistor M5 and the N type channel transistor M6. Consequently, after the N type channel transistor M6 whose current drive capacity is larger than, the P type channel transistor M5 is turned to ON state, the P type channel transistor M5 is turned to OFF state. Thus, a gate voltage G2 of the N type channel transistor M2 is fixed to a low level voltage so as to turn the N type channel transistor M2 to OFF state in a period of time 0 to t1 as shown in the Figure.
In the above-mentioned buffer circuit 100, after the N type channel transistor M2 is turned to OFF state, the P type channel transistor M1 is turned to ON state by an operation described below. In the meantime, reference numeral 42 denotes an inverter. As described above, if the low level enable signal is inputted from the enable control input terminal (IN2) and the high level data signal is inputted from the data input terminal (IN1), a NOR gate circuit NOR outputs a high level signal to each gate of the P type channel transistor M3 and the N type channel transistor M4. Consequently, after the P type channel transistor M3 whose current drive capacity is larger than the N type channel transistor M4 is turned to OFF state, the N type channel transistor M4 is turned to ON state. Thus, a gate voltage G1 of the P type channel transistor M1 is fixed to a low level voltage so as to turn the P type channel transistor M1 to ON state in a period of time 0-t1 as shown in the Figure.
As described above, in the buffer circuit 100, the both transistors M1, M2 are not turned to ON state at the same time because the P type channel transistor M1 is turned to ON state after the N type channel transistor M2 is turned to OFF state thereby preventing any through current from flowing to the both transistors M1 and M2.